1. Field
Apparatuses and methods consistent with exemplary embodiments relate to arrangement of pads in a semiconductor device, and more particularly, to a method of arranging pads in a semiconductor device, a semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device includes pads for enabling electrical connection with external devices. Signals associated with operations, such as command input, data read, and data write, are input to or output from the semiconductor memory device through the pads.
Manufacturing methods for semiconductor memory devices have become highly integrated, thereby reducing the size of the semiconductor memory device and reducing the production cost.
Although the degree of integration of devices mounted in a semiconductor memory device has doubled, the number of pads may or may not be increased. Conversely, if the degree of integration is reduced by half, the number of pads may or may not be decreased. Thus, in a high-integration memory device, the area of the pads is not an issue, but for a low-integration memory device, the area of the pads may be an issue. This is because, with the development of semiconductor device manufacturing technology, the chip size has been continuously decreasing while the pad size has decreased in a corresponding manner. In other words, despite of the reduction in overall chip size, pad size has not been reduced.
Thus, the rate of reduction in an interval between the pads or the pad size has not corresponded to the rate of increase in the degree of integration of the semiconductor memory devices. As a result, there is a related art overhead in the chip size due to the size of the pads, especially for low-integration memory devices.